Journal des systèmes électriques et électroniques

The three-dimensional missile guidance law with saturating actuator is proposed for the pursuit of an unpredictably maneuvering target. The proposed guidance law achieves a satisfactorily robust performance without having to solve a complicated nonlinear Hamilton-Jacobi Partial Differential Inequality (HJPDI). In the proposed guidance scheme, the nonlinear part of the relative motion equations between the missile and target is first cancelled. Then, a tunable sliding mode law is designed to eliminate the effect of external disturbance. The proposed guidance law can achieve reduced interception time than others, yet it is considerably simpler. An example is proposed to confirm it.

Brushless DC Motors (BLDCM) are widely used in automated industrial applications like Computer Numerical Control (CNC) machinery, aerospace applications and in the field of robotics. But it still suffers from commutation torque ripple, which mainly depends on speed and transient line current in the commutation interval. This work presents a new circuit topology and a DC link voltage control strategy to keep incoming and outgoing phase currents changing at the same rate during commutation. A Single-Ended Primary Inductor Converter (SEPIC) and a switch selection circuit are employed in front of the inverter. The desired commutation voltage is accomplished by the SEPIC converter. The cause of commutation ripple is analyzed, and the way to obtain the desired DC link voltage is introduced in detail. Finally, simulation results show that, compared with the DC-DC converter, the proposed method can obtain the desired voltage much faster and minimize commutation torque ripple more efficiently at both high and low speeds.

Time-mode circuits where information is represented by the timing difference of digital signals possess a number of intrinsic characteristics that are scaled well with CMOS technology, making them a promising and viable option to implement some of the key building blocks of mixed analog-digital subsystems Analog-to-Digital Converters (ADCs) and Phase-Locked Loops (PLLs). This paper examines the challenges encountered in analog design with technology scaling and presents the fundamental advantages of time-mode circuits. It investigates the building blocks of timemode circuits for mixed analog-digital signal processing with a special focus on ADCs.