Système et gestion des télécommunications

Performance Analysis of Array Multipliers Using Different Logic Configurations

Abstract

Swetha BN and Satish Kumar B

Power and speed are the two important design aspects that impact the designing of any circuits. One of the most widely used arithmetic operations in digital circuits is multiplication. There are different multipliers designed depending on the speed and the hardware. There are different technologies with different features. In this paper 4-bit and 8-bit array multipliers are been designed using different designing techniques. The multipliers are designed using CMOS logic configuration, pseudo-NMOS logic configuration and transmission gate logic configuration and are compared in terms of power and delay. The power delay product (PDP) gives the overall performance of the Multipliers.